This invention relates generally to integrated circuits and more particularly to electrostatic discharge (ESD) protection circuits.
Electrostatic discharge (ESD) is known to damage electronic circuitry, especially integrated circuits (IC). As is known, ICs that are fabricated using smaller processing techniques (e.g. 0.25 micron technology) are more susceptible to being damaged by ESD than ICs that are fabricated using a larger processing technique (0.5 micron technology). To minimize damage due to ESD, ICs are manufactured, shipped, and handled in special ways. For example, ICs are typically shipped in tubes that protect against ESD. In addition, persons handling the integrated circuits wear ESD wrist straps to protect against ESD.
While manufacturing, shipping, and handling ESD protection techniques reduce the risk of ESD damage to ICs, the risk is not eliminated. To further reduce the risk of ESD damage, many integrated circuits include ESD protection circuits. Such ESD protection circuits include an ESD sensing circuit and a clamp. The clamp is typically a transistor that is coupled between VDD (the positive supply voltage pin) and VSS (the negative supply voltage pin). The clamping transistor is triggered by one of a variety of ESD sensing circuits.
One simple ESD sensing circuit incorporates a resistor-capacitor (RC) circuit, which, based on the time constant of the RC circuit, will detect an ESD event. A difficulty arises with such an ESD sensing circuit when used with high-speed digital circuitry. For example, if the RC time constant is set to high (e.g. to avoid false triggering due to the high speed digital switching), an ESD event may not be recognized until damage has occurred. If, on the other hand, the RC time constant is set too low (e.g. to ensure proper detection of an ESD event) false triggering may result when used in a high-speed digital switching circuits.
To overcome the false triggering problem, some ESD sensing circuits implement a smaller resistor-capacitor (RC) time constant, which delays the activation of the clamping transistor such that false triggering is minimized. While this protects against false triggering, it slows the responsiveness of the ESD protection circuit and requires additional circuitry.
Therefore, a need exists for an ESD protection circuit that is not susceptible to false triggering in high-speed digital circuits, is very responsive to ESD events, and does not require additional false triggering compensation circuitry.